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July 17 2014

Chip Shot: Intel Delivering Customized Silicon for Enterprise Solutions

Intel has created a customized SKU based on its latest Intel® Xeon® processor E7 v2 family that, when coupled with Oracle software enhancements, allows Oracle to deliver an “elastic compute environment.”  The solution requires customization of the Intel Xeon processor E7 v2 SKU as well as software changes that enable the Oracle application to dynamically scale the frequency and number of cores to maximize performance. Disclosure of this work was made today at the announcement of Oracle’s new Exadata Database Machine X4-8. This is another example of Intel providing optimized solutions for its partners to address specific workload needs, in this case for enterprise customers.

July 10 2014

Chip Shot: Intel® Xeon® and Intel® Xeon Phi™ Processors to Power Next Generation, Multi-Petaflop Cray Supercomputer Deployment at NNSA

Cray Inc. today announced it has been awarded a $174 million contract to provide the National Nuclear Security Administration (NNSA) with a multi-petaflop supercomputing system powered by future Intel® Xeon® processors code-named “Haswell” and future Intel® Xeon Phi™ processors code-named “Knights Landing.” The system, named “Trinity” by the NNSA, will provide the NNSA with a world-class supercomputer for ensuring the safety, security and effectiveness of the United States’ nuclear stockpile. Intel Xeon and Intel Xeon Phi processors will provide Trinity with the superior combination of performance, programmability and reliability needed to advance the mission for the agency’s stockpile stewardship program. Visit the Cray and NNSA releases to learn more.

July 01 2014

Chip Shot: Intel and DreamWorks Animation* Team up on “How to Train Your Dragon 2″

The new movie “How to Train Your Dragon 2” is the first that was developed using a new animation platform created by DreamWorks Animation*.Intel worked extensively with DreamWorks on two elements of that platform, PrEMO and Torch. The two tools are built-from-the-ground-up animation and lighting applications that give animators instantaneous feedback on changes made to a scene. These tools were built to ensure all aspects of the hardware and software were optimized to take advantage of the power of each core in Intel’s processors. Want to learn more? Check out the details.

June 23 2014

Chip Shot: Intel Announces New HPC Fabrics and Reveals Details of Next Generation Processors

Today at the International Supercomputing Conference in Leipzig, Germany, Intel unveiled details on the next-generation Intel® Xeon Phi™ processor  codenamed Knights Landing, which includes the newly integrated Intel® Omni Scale Fabric, an end-to-end interconnect optimized for fast data transfers and better efficiency. Knights Landing will feature high-bandwidth on-package memory and deliver up to three times the performance of the prior generation while using less energy. Intel technology was also showcased throughout the conference with Intel® Xeon® processors powering 85% of systems in the newly published TOP500 list, underscoring their role as the fundamental building block for the world’s most powerful supercomputers. The press release, Dr. Rajeeb Hazra’s ISC keynote, videos and other information on this news is available here.

June 23 2014

Chip Shot: Intel Announces New HPC Fabrics and Reveals Details of Next Generation Processors

Today at the International Supercomputing Conference in Leipzig, Germany, Intel unveiled details on the next-generation Intel® Xeon Phi™ processor  codenamed Knights Landing, which includes the newly integrated Intel® Omni Scale Fabric, an end-to-end interconnect optimized for fast data transfers and better efficiency. Knights Landing will feature high-bandwidth on-package memory and deliver up to three times the performance of the prior generation while using less energy. Intel technology was also showcased throughout the conference with Intel® Xeon® processors powering 85% of systems in the newly published TOP500 list, underscoring their role as the fundamental building block for the world’s most powerful supercomputers. The press release, Dr. Rajeeb Hazra’s ISC keynote, videos and other information on this news is available here.

June 23 2014

Chip Shot: Latest Intel Lustre Software Offers Fast, Scalable Storage

At the International Supercomputing Conference today, Intel announced the latest release of the Intel® Enterprise Edition for Lustre software that combines the performance and scalability of open-source Lustre software with new tools to help IT use Lustre storage for the most data-intensive applications. Building on the Lustre 2.5 foundation, the Intel Enterprise Edition for Lustre features new capabilities to monitor vast amounts of dynamic data to identify and overcome performance constraints as well as larger sized configurations to meet the need for faster and more productive storage solutions. Additionally, the latest version includes a new Lustre client for Intel® Xeon Phi™ coprocessors that delivers 10 times improved streaming I/O compared to network file systems. To learn more, visit lustre.intel.com.

June 23 2014

Intel Re-architects the Fundamental Building Block for High-Performance Computing

Next-Generation Intel® Xeon Phi™ Processor with Integrated Intel® Omni Scale Fabric to Deliver Up to 3 Times the Performance of Previous Generation at Lower Power

NEWS HIGHLIGHTS

  • Announces new microarchitecture and memory details of the next-generation Intel® Xeon Phi™ processor (code-named Knights Landing), scheduled to power HPC systems in the second half of 2015.
  • Intel® Omni Scale Fabric– an end-to-end interconnect optimized for fast data transfers, reduced latencies and higher efficiency – initially available as discreet components in 2015, will also be integrated into next-generation Intel Xeon Phi processor (Knights Landing) and future 14nm Intel® Xeon® processors.
  • Intel continues to lead in HPC segment with 85 percent of all supercomputers on the latest TOP500* list powered by Intel Xeon processors.

INTERNATIONAL SUPERCOMPUTING CONFERENCE (ISC), Leipzig, Germany, June 23, 2014 – Intel Corporation today announced new details for its next-generation Intel® Xeon Phi™ processors, code-named Knights Landing, which promise to extend the benefits of code modernization investments being made for current generation products. These include a new high-speed fabric that will be integrated on-package and high-bandwidth, on-package memory that combined, promise to accelerate the rate of scientific discovery. Currently memory and fabrics are available as discrete components in servers limiting the performance and density of supercomputers.

The new interconnect technology, called Intel® Omni Scale Fabric, is designed to address the requirements of the next generations of high-performance computing (HPC). Intel Omni Scale Fabric will be integrated in the next generation of Intel Xeon Phi processors as well as future general-purpose Intel® Xeon® processors. This integration along with the fabric’s HPC-optimized architecture is designed to address the performance, scalability, reliability, power and density requirements of future HPC deployments. It is designed to balance price and performance for entry-level through extreme-scale deployments.

“Intel is re-architecting the fundamental building block of HPC systems by integrating the Intel Omni Scale Fabric into Knights Landing, marking a significant inflection and milestone for the HPC industry,” said Charles Wuischpard, vice president and general manager of Workstations and HPC at Intel. “Knights Landing will be the first true many-core processor to address today’s memory and I/O performance challenges. It will allow programmers to leverage existing code and standard programming models to achieve significant performance gains on a wide set of applications. Its platform design, programming model and balanced performance makes it the first viable step towards exascale.”

Knights Landing – Unmatched Integration
Knights Landing will be available as a standalone processor mounted directly on the motherboard socket in addition to the PCIe-based card option. The socketed option removes programming complexities and bandwidth bottlenecks of data transfer over PCIe, common in GPU and accelerator solutions. Knights Landing will include up to16GB high-bandwidth, on-package memory at launch – designed in partnership with Micron* – to deliver five times better bandwidth compared to DDR4 memory1, five times better energy efficiency2 and three times more density2 than current GDDR-based memory. When combined with integrated Intel Omni Scale Fabric, the new memory solution will allow Knights Landing to be installed as an independent compute building block, saving space and energy by reducing the number of components.

Powered by more than 60 HPC-enhanced Silvermont architecture-based cores, Knights Landing is expected to deliver more than 3 TFLOPS of double-precision performance3 and three times the single-threaded performance4 compared with the current generation. As a standalone server processor, Knights Landing will support DDR4 system memory comparable in capacity and bandwidth to Intel Xeon processor-based platforms, enabling applications that have a much larger memory footprint. Knights Landing will be binary-compatible with Intel Xeon processors5, making it easy for software developers to reuse the wealth of existing code.

For customers preferring discrete components and a fast upgrade path without needing to upgrade other system components, both Knights Landing and Intel Omni Scale Fabric controllers will be available as separate PCIe-based add-on cards. There is application compatibility between currently available Intel® True Scale Fabric and future Intel Omni Scale Fabric, so customers can transition to new fabric technology without change to their applications. For customers purchasing Intel True Scale Fabric today, Intel will offer a program to upgrade to Intel Omni Scale Fabric when it’s available.

Knights Landing processors are scheduled to power HPC systems in the second half of 2015. For instance, in April the National Energy Research Scientific Computing Center (NERSC) announced an HPC installation planned for 2016, serving more than 5,000 users and over 700 extreme-scale science projects.

“We are excited about our partnership with Cray and Intel to develop NERSC’s next supercomputer ‘Cori,’” said Dr. Sudip Dosanjh, NERSC Director, Lawrence Berkeley National Laboratory. “Cori will consist of over 9,300 Intel Knights Landing processors and will serve as an on-ramp to exascale for our users through an accessible programming model. Our codes, which are often memory-bandwidth limited, will also greatly benefit from Knights Landing’s high speed on package memory. We look forward to enabling new science that cannot be done on today’s supercomputers.”

New Fabric, New Speeds with Intel Omni Scale Fabric
Intel Omni Scale fabric is built upon a combination of enhanced acquired IP from Cray and QLogic, and Intel’s own in-house innovations. It will include a full product line offering consisting of adapters, edge switches, director switch systems, and open-source fabric management and software tools. Additionally, traditional electrical transceivers in the director switches in today’s fabrics will be replaced by Intel® Silicon Photonics-based solutions, enabling increased port density, simplified cabling and reduced costs6. Intel Silicon Photonics-based cabling and transceiver solutions may also be used with Intel Omni Scale-based processors, adapter cards and edge switches.

Intel Supercomputing Momentum Continues
The current generation of Intel Xeon processors and Intel Xeon Phi coprocessors powers the top-rated system in the world – the 35 PFLOPS “Milky Way 2″ in China. Intel Xeon Phi coprocessors are also available in more than 200 OEM designs worldwide.

Intel-based systems account for 85 percent of all supercomputers on the 43rd edition of the TOP500 list announced today and 97 percent of all new additions. Within 18 months after the introduction of Intel’s first many-core architecture products, Intel Xeon Phi coprocessor-based systems already make up 18 percent of the aggregated performance of all TOP500 supercomputers. The complete TOP500 list is available at www.top500.org.

To help optimize applications for many-core processing, Intel has also established more than 30 Intel Parallel Computing Centers (IPCC) in cooperation with universities and research facilities around the world. Today’s parallel optimization investment with the Intel Xeon Phi coprocessor will carry forward to Knights Landing, as optimizations using standards-based, common programming languages persist with a recompile. Incremental tuning gains will be available to take advantage of innovative new functionality.

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About Intel
Intel (NASDAQ: INTC) is a world leader in computing innovation. The company designs and builds the essential technologies that serve as the foundation for the world’s computing devices. As a leader in corporate responsibility and sustainability, Intel also manufactures the world’s first commercially available “conflict-free” microprocessors. Additional information about Intel is available at newsroom.intel.com and blogs.intel.com and about Intel’s conflict-free efforts at conflictfree.intel.com.

Intel, Xeon, Intel Xeon Phi, Intel Atom and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States or other countries.

*Other names and brands may be claimed as the property of others.

All products, computer systems, dates and figures specified are preliminary based on current expectations, and are subject to change without notice.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined”. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Intel’s compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2®, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products.

Results have been measured by Intel based on software, benchmark or other data of third parties and are provided for informational purposes only. Any difference in system hardware or software design or configuration may affect actual performance. Intel does not control or audit the design or implementation of third party data referenced in this document. Intel encourages all of its customers to visit the websites of the referenced third parties or other sources to confirm whether the referenced data is accurate and reflects performance of systems available for purchase”

1 Projected result based on internal Intel analysis of STREAM benchmark using a Knights Landing processor with 16GB of high-bandwidth versus DDR4 memory only with all channels populated

2 Projected results based on internal Intel analysis of Knights Landing’s on-package memory MCDRAM vs Knights Corner’s GDDR5 memory

3 Internal and preliminary projections of theoretical double-precision performance measured by Linpack. Based on current expectations of Knights Landing’s cores, clock frequency and floating point operations per cycle.

4. Projected peak theoretical single-thread performance relative to 1st Generation Intel® Xeon Phi™ Coprocessor 7120P (formerly code-named Knights Corner)

5 Binary Compatible with Intel Xeon processors using Haswell Instruction Set (except TSX – Transactional Synchronization Extensions)

6 The TCO or other cost reduction scenarios described in this document are intended to enable you to get a better understanding of how the purchase of a given Intel product, combined with a number of situation-specific variables, might affect your future cost and savings. Circumstances will vary and there may be unaccounted-for costs related to the use and deployment of a given product. Nothing in this document should be interpreted as either a promise of or contract for a given level of costs.”

June 18 2014

Chip Shot: Disrupting the Data Center with Customizable Chips

At the Gigaom Structure conference in San Francisco today, Intel’s Diane Bryant announced that the company will now offer customizable chips for the data center based on industry leading Intel® Xeon® processors. For the first time, Intel server customers will be able to incorporate their own software and IP via a field-programmable gate array (FPGA) integrated into the same package, which can be programmed for specific functions and workloads, like search or video compression, particularly as the patterns change. This is an example of Intel leading a massive transformation at the silicon level of the data center to drive increased value to our customers.

May 28 2014

Chip Shot: Intel® Xeon Phi™ Momentum Continues; Issues New Call to Expand Intel Parallel Computing Centers

Solving some of the biggest challenges in society, industry, and sciences requires dramatic increases in computing efficiency. To address this, Intel introduced the Intel® Parallel Computing Center (IPCC) program last October with five collaborators. Since then, the response has been outstanding with more than 30 IPCCs worldwide today. Now, Intel is announcing a new call for IPCC proposals to join in delivering open, portable, and scalable applications that focus on the untapped potential of high performance computing capabilities and accelerate discovery. To learn more, read the blog post by Intel’s Bob Burroughs, director of ecosystem enabling for the Technical Computing Group.

May 12 2014

Chip Shot: Intel Updates Server Boards and Systems for Intel® Xeon® Product Family

The Intel® Server Boards and Systems that support the Intel® Xeon® Processor E3-1200 V3 family can support the newly announced processor SKUs with a BIOS update once the chips are available. Additionally, The Product Collaboration and Syst…